I wanted to share with you couple of highly recommended UVM books. You may prefer to refer these books to enhance your knowledge about the SystemVerilog & UVM based Testbench Architecture Development & learning many more features. I believe, you’ll find it useful.

UVM Books:

1. SystemVerilog For Verification: A Guide to Learning the Testbench Language Features by Chris Spear & Greg Tumbush (3rd Edition)

2. A Practical Guide to Adopting Universal Verification Methodology (UVM) by Sharon Rosenberg & Kathleen A Meade (2nd Edition)

3. The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology by Ray Salemi

4. Getting Started with UVM: A Beginner’s Guide by Vanessa R. Copper

5. A Practical Guide For SystemVerilog Assertions by Srikanth Vijayaraghavan & Meyyappan Ramanathan

6. UVM Cookbook

7. UVM Golden Reference Guide